Many if not most of the integrated circuits which are being produced today comprise some number of clocked logic gates. A clocked logic gate is one which performs its function subsequent to the assertion (or deasertion) of a clock signal.
For example, some logic gates (e.g., some static logic gates) receive a clocked enable signal and cannot perform their intended functions until the enable signal is asserted. Such a clock enabled logic gate 100 is illustrated in FIG. 1.
Other logic gates (e.g., some dynamic logic gates) are alternately precharged and enabled by a clock signal, and can only perform their intended functions during the enable phase of the clock signal. A precharged logic gate 200 is illustrated in FIG. 2 and comprises a precharger 202, a logic block 204 for evaluating a desired logic function, and an inverting buffer 206.
Clocked logic gates 100, 200 are often interdependent on one another. For example, FIG. 3 illustrates a logic pipeline 300 in which data is alternately clocked through stages 304, 308, 312 of the pipeline 300. FIG. 4 illustrates two bodies of logic 402, 404 that generate data which is then combined in a later logic stage 406 (e.g., the two bodies of logic 402, 404 might respectively generate two addends which are input to an adder 406).
In each of the scenarios presented in FIGS. 3 & 4, the interdependence of the clocked logic gates requires an orderly and timely progression of data. Absent an orderly and timely progression of data through the logic pipeline 300 which is illustrated in FIG. 3, or the logic junction 400 which is illustrated in FIG. 4, data flowing through clocked logic gates 100, 200 is likely to be corrupted.
Typically, the orderly and timely progression of data through clocked logic gates 100, 200 is regulated by a pair of out-of-phase clocks. For example, the first of the clocks might cause data to propagate through odd logic stages 304, 312 of a pipeline 300 at multiples of time T, and the second of the clocks might cause data to propagate through even logic stages 308 of the pipeline 300 at multiples of time T+X, where X is not a multiple of T.
Theoretically, clocked logic gates 100, 200 should be able to be clocked with two clocks which are exactly 180.degree. out-of-phase (e.g., clocks CK1 and CK2 in FIG. 5). However, real world conditions such as wire resistance, switching time, capacitance, clock skew, and clock edge degradation often prohibit the alternate clocking of sequential, clocked logic blocks 402, 406 (or logic stages 304, 308, 310) with 180.degree. out-of-phase clocks. The problem with such a clocking scheme is that in many situations, a "race" is possible as soon as pulses of the two clocks start to overlap. A race is a condition in which data tends to propagate through more than one sequential, clocked logic block 402, 406 during a single clock period. Oftentimes, a race occurs as a result of data propagating through two or more sequential memory elements 302, 306, 310 during a single clock period.
Races may take a variety of forms, depending upon the configuration of the clocked logic blocks 100, 200 involved. For example, refer to the logic pipeline 300 illustrated in FIG. 3. If clock CK2N is not de-asserted prior to the assertion of clock signal CK1N, data being processed in LOGIC STAGE_1 can race through LATCH 1 and corrupt necessary data which has yet to be output from LOGIC STAGE_2. With respect to FIG. 4, a race can occur, for example, if new data propagates through LOGIC BLOCK_2 and overwrites the value of DATA_2 prior to the previous and required value of DATA_2 being consumed by LOGIC BLOCK_3.
From the above examples, one can see that when upstream data wins a race and catches up with downstream data, it is very likely that the downstream data will be corrupted. Race prevention is therefore critical to the effective operation of clocked logic gates 100, 200.
One way to prevent races is by alternately clocking sequential, clocked logic blocks 402, 406 with a pair of non-overlapping clocks. Such a pair of non-overlapping clocks is illustrated in FIG. 5 as clocks CK1N and CK2N. Note that between the pulses of each clock there is a "deadtime" during which neither of the clocks is asserted. A first deadtime 502 lies between the falling edge 520 of clock CK1N and the rising edge 516 of clock CK2N, and a second deadtime 500 lies between the falling edge 522 of clock CK2N, and the rising edge 512 of clock CK1N. Since deadtimes 500, 502 are times in which little or no useful work is done, it is important to adjust the deadtimes between non-overlapping clocks so that they are just long enough to prevent races from occurring, but no longer.
One way to produce out-of-phase clocks such as CK1, CK2, CK1N and CK2N (FIG. 5) is via a system 600 of clock gaters 602, 604, 606, 608 (FIG. 6). A clock gater 602, 604, 606, 608 is merely a circuit which receives a first clock signal and outputs a second clock signal, which second clock signal is out-of-phase with the first clock signal in one or more ways. For example, the pulses of the second clock signal may have rising and/or falling edges which are out-of-phase with the rising and falling edges of the first clock signal, or the pulses of the second clock signal may be of shorter or longer duration than those of the first clock signal.
A number of exemplary clock gater circuits are disclosed in U.S. Pat. No. 5,124,572 of Mason et al. entitled "VLSI Clocking System Using Both Overlapping and Non-overlapping Clocks", U.S. Pat. No. 5,306,962 of Lamb entitled "Qualified Non-Overlapping Clock Generator to Provide Control Lines with Non-Overlapping Clock Timing", U.S. Pat. No. 5,726,596 of Perez entitled "High-Performance, Low-Skew Clocking Scheme for Single-Phase, High-Frequency Global VLSI Processor Clocks", and U.S. Pat. No. 5,760,610 of Naffziger entitled "Qualified Universal Clock Buffer Circuit for Generating High Gain, Low Skew Local Clock Signals". These patents are hereby incorporated by reference for all that they disclose.
The patents of Mason et al. and Lamb disclose a clocking methodology for VLSI circuits which selectively uses the edges of two overlapping clocks and two non-overlapping clocks to eliminate race conditions. The overlapping clocks are used wherever possible to provide superior timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. The patents of Perez and Naffziger disclose various improvements to the clocking methodologies disclosed in Mason et al. and Lamb.
Although all of the clock gater circuits disclosed in the above-referenced patents produce a pair of non-overlapping clocks, it is not particularly easy to adjust the deadtimes between any of these clocks. Doing so requires the resizing of clock gater transistors for the purpose of adding or subtracting from a deadtime. However, once appropriate transistors have been resized for the purpose of adjusting a deadtime, other transistors may need to be resized for the purpose of balancing loads, etc. Still other transistors may need to be resized if, for example, it is desired that the falling edges of clocks CK1 and CK1N fall in unison, or if it is desired that the falling edges of clocks CK2 and CK2N fall in unison.
A clock gater circuit which may be easily tuned for the purpose of adjusting the deadtime between non-overlapping clock signals is therefore needed.